A small, light weight, RISC CPU soft core

Bus bridges and other odds and ends

Code generation tool for control and status registers

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

A simple, basic, formally verified UART controller

A utility for Composing FPGA designs from Peripherals

An Open Source configuration of the Arty platform

Simple UART controller for FPGA written in VHDL

A wishbone controlled scope for FPGA's

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Wishbone controlled I2C controllers

CMod-S6 SoC

A collection of debugging busses developed and presented at zipcpu.com

RMII Firewall FPGA

A wishbone controlled FM transmitter hack

CERES: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

RISC-V Ibex core with Wishbone B4 interface

A System on a Chip Implementation for the XuLA2-LX25 board

Trying to learn Wishbone by implementing few master/slave devices

Forth CPU J1 in SystemVerilog and Wishbone interface

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

A collection of formal properties for hardware buses, and cores using them.

Trying to implement a soft core SoC

A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91

VHDL implementation of Pipelined Wishbone B4 interconnect

Check Wishbone B4 variants

Plasma MIPS (I) SoC

A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.

SymbiYosys (sby) Formal Verification

VHDL SPI slave, providing Wishbone bus master