ZI

ZipCPU/wbuart32

A simple, basic, formally verified UART controller

fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus

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Languages

Verilog74.8%C++14.7%Makefile7.7%Perl2.4%HTML0.4%

Contributors

GNU General Public License v3.0

Created September 21, 2016

Updated March 8, 2026

ZipCPU/wbuart32 | GitHunt