Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

微电子和集成电路自学指南

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Microshift Compression: An Efficient Image Compression Algorithm for Hardware

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Gatery, a library for circuit design.

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Spiking Neural Network Accelerator

Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)

Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

32-bit RISC-V microcontroller

The Repository contains the code of various Digital Circuits

UART - RTL Design and Verification

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

A tool to compile your RTL files into GDSII layouts.

We are designing a CP-PLL. The following link provides resources about PLL design.

This is part of EC383 - Mini Project in VLSI Design.

"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.