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UART-protocol

UART - RTL Design and Verification
UART protocol is designed and the same is verified effectively using testbench. Design part involves designing of all the submodules of transmitter and receiver sections, FSM,parity generator and clock divider. In verification, different test cases are used to verify the working operation of the design.

Languages

Verilog100.0%

Contributors

Created August 30, 2021
Updated February 12, 2026
mnmhdanas/UART-protocol | GitHunt