cocotb: Python-based chip (RTL) verification

Functional verification project for the CORE-V family of RISC-V cores.

Fun, portable, minimalistic virtual machine.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

AMBA AXI VIP

Code generation tool for control and status registers

Awesome ASIC design verification

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Network on Chip Implementation written in SytemVerilog

Control and status register code generator toolchain

VIP for AXI Protocol

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

A Framework for Design and Verification of Image Processing Applications using UVM

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

:snail:Yet Another Simulation Architecture

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

Generate UVM register model from compiled SystemRDL input

UVM Testbench to verify serial transmission of data between SPI master and slave

Universal Virtual Machine for Node and Browser

UVM Generator

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

A simple UVM example with DPI

Customized UVM Report Server

my UVM training projects

This serves as a repository for reproducibility of the SC21 paper "In-Depth Analyses of Unified Virtual Memory System for GPU Accelerated Computing," as well as several components of the IPDPS21 paper "Demystifying GPU UVM Cost with Deep Runtime and Workload Analysis."

SystemVerilog UVM testbench example