Network on Chip Implementation Written in SystemVerilog

Overview

This is a Network on Chip (NoC) Router/Fabric implementation written in SystemVerilog. It has following features.

• 2-D mesh network
• Dimension order routing (X-Y routing)
• Flow control
  • Wormhole (FLIT based) flow control
  • Virtual channel flow control
  • On/Off Flow control
• Configurable design
  • Packet format
  • Mesh size
  • FIFO size
  • etc.
• Support standard bus protocol
  • AMBA AXI4

Details

TBW

Contact

If you have any problems, questions, ideas, etc., you can post them on the following ways.

1. Issue Tracker
2. Chat Room
3. Mail

Copyright

Copyright (c) 2017-2018 Taichi Ishitani. See LICENSE for further details.