RISC-V CPU Core (RV32IM)

A self-hosting and educational C optimizing compiler

32-bit Superscalar RISC-V CPU

Simple 3-stage pipeline RISC-V processor

Trivial RISC-V Linux binary bootloader

A web-based RISC-V simulator https://riscv-simulator-five.vercel.app

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

miniSpartan6+ (Spartan6) FPGA based MP3 Player

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Some materials and sample source for RV32 OS projects.

32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.

RISC-V ISA emulator

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zimop Zba Zbb Zbs Sdext Sdtrig microcontroller

Verilog-based single-cycle CPU implementing the RV32IM instruction set. Supports integer and multiplication/division instructions with modular design, ALU, control unit, and UART-based debugging.

Becoming acquainted with the RISC-V ISA by writing an emulator

A minimalist monolithic OS kernel for the RISC-V 32-bit architecture. An educational project demonstrating core concepts like multitasking, virtual memory, and system calls.

RV32IM System-on-Chip (SoC)

A synthesizable RISC-V RV32IM microcontroller written in VHDL

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards

Softcore microcontroller with peripherals based on PicoRV32

A simple RV32I RISC-V CPU emulator in C++ supporting: ADDI, ADD, SUB, MUL, MULH, SRAI , LW, SW, LUI, JAL , ECALL (program exit) - ELF loader for test programs ,Instruction trace for debugging

A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.

RISC-V emulator written in Rust. Features a TUI interface and RV32IMAC support.

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

Simple bash script for building GNU riscv32-unknown-elf-gcc newlib toolchain.

sysy lang by c executable in risc-v platform.

Emulation, implementation and verification of RISC-V core with I,M and Zbb extensions