RISC-V CPU

A 6-stage pipelined RISC-V processor core designed for FPGA deployment, featuring an integrated UART controller for system programming and debugging. Achieved 263.7 CoreMark and 91.0 DMIPS at 100 MHz.

Features

ISA Support

• Base ISA: RV32I (RISC-V 32-bit Integer Base Instruction Set)
• Extensions:
  • M: Integer Multiplication and Division
  • Zicsr: Control and Status Register (CSR) Instructions
  • Zifencei: Instruction-Fetch Fence (FENCE.I)

Microarchitecture

• Pipeline: 6-stage (Fetch, Decode, Execute, Memory 1, Memory 2, Writeback)
  • MEM1: Memory Access & Store Align
  • MEM2: Data Ready (FPGA BRAM Latency) & Load Data Extend
• Branch Prediction:
  • BHT (Branch History Table): 256 entries. Uses a 2-bit Saturating Counter (Strongly/Weakly Taken/Not Taken) to predict conditional branches. Implemented as LUTRAM.
  • BTB (Branch Target Buffer): 256 entries. Stores Valid bit, Entry Type (Branch, Jump, Return), Tag, and Target Address. Implemented as LUTRAM.
  • RAS (Return Address Stack): 32 entries. Push on JAL/JALR with call hint (CFHINT_CALL); pop on JALR with return hint (CFHINT_RET). Supports nested function calls.
  • Prediction Logic: For branches, pred_taken = bht_taken && btb_hit; for JAL/JALR, pred_taken = btb_hit. No pipeline stalls or flushes on a correct prediction.
• Branch Resolution:
  • Branch Unit: Resolution & validation in EX stage. Registers inputs for timing optimization (1-cycle latency).
  • Recovery: 3-cycle penalty on misprediction (Flush ID/EX/MEM1, redirect PC)
• Hazard Handling:
  • RAW hazards resolved by forwarding from MEM1/MEM2/WB to EX
  • Store-Data hazards resolved by forwarding from WB to MEM1
  • Load-Use hazards resolved by 2-cycle pipeline stall + WB to EX forwarding
  • Branch Misprediction resolved by pipeline flush
• Trap/Exception Support:
  • ECALL, EBREAK, MRET
  • Illegal Instruction
  • Instruction/Data Address Misalign
  • Instruction/Data Access Fault
• Hardware Multiplier & Divisor:
  • Multiplier: Implemented using inferred DSP blocks (via (* use_dsp = "yes" *) synthesis attribute).
  • Divisor: Implemented using a custom iterative shift-subtract logic (2x loop unrolled, 16 cycles for 32-bit division).

Clock Domain and Reset

Target FPGA

• Board: ALINX AX7Z020B (Zynq-7020)
• Input Clock: 50 MHz (onboard oscillator)
• Internal Clock: 100 MHz (via MMCM)

Clock and Reset Signals

Reset Behavior

1. Hard Reset: Physical button or MMCM lock.
2. Soft Reset: Controlled via UART commands during programming.
3. Initialization: PC resets to 0x00000000, pipeline flushes.

Memory Specifications

Memory Map

Instruction Memory (IMEM)

• Size: 128 KB (32768 words)
• Width: 32-bit
• Access: Read-only; writable via UART programmer (runtime, without FPGA reconfiguration)

Data Memory (DMEM)

• Size: 128 KB (32768 words)
• Width: 32-bit
• Access: Read/Write (byte-enable write strobe)
• IO Mapping:
  • Writes to 0xFFFF_0000 (PRINT_ADDR) with data[8] == 0 → RES_PRINT via UART TX.
  • Writes to 0xFFFF_0000 with data[8] == 1 → RES_EXIT with data[7:0] as exit code.
  • Reads from 0xFFFF_0004 (INPUT_ADDR) → returns input_data if RX FIFO non-empty, else 0xFFFFFFFF. Polled by getchar() in syscalls.
• Access Fault: Accesses outside the DMEM range (other than PRINT_ADDR and INPUT_ADDR) trigger a Data Access Fault trap.

Performance Characteristics

CoreMark Benchmark

Measured on Zynq-7020 FPGA running at 100 MHz (RV32IM, -O2, ITERATIONS=3000).

Dhrystone 2.2 Benchmark

Measured on Zynq-7020 FPGA running at 100 MHz (RV32IM, -O2, NUMBER_OF_RUNS=100000).

DMIPS = Dhrystones/Second ÷ 1,757 (VAX 11/780 reference = 1 DMIPS)

Hardware Multiplier & Divisor

Multiplier

• Inferred DSP48 blocks via (* use_dsp = "yes" *) synthesis attribute.
• 3-stage pipeline: result available 3 cycles after issue, causing a 3-cycle stall (MUL_COUNT = 3).

Divisor

• Algorithm: Shift-compare-subtract. Handles signed/unsigned division and remainder, with special-case handling for divide-by-zero and signed overflow.
• 2x loop unrolled: computes 2 quotient bits per clock cycle combinatorially.
• 32-bit division takes 17 cycles total (1 setup + 16 compute), causing a 17-cycle stall (DIV_COUNT = 17, SHIFT_COUNT = 16).

Pipeline Performance

• Ideal CPI: 1.0
• Actual CPI: Depends on program characteristics (typically 1.1–1.5 due to hazards)

Hazard Penalties

Trap/Exception Penalties

Supported Instructions

RV32I Base Integer Instructions

• Arithmetic: ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU
• Immediate Arithmetic: ADDI, ANDI, ORI, XORI, SLLI, SRLI, SRAI, SLTI, SLTIU
• Load: LB, LH, LW, LBU, LHU
• Store: SB, SH, SW
• Branch: BEQ, BNE, BLT, BGE, BLTU, BGEU
• Jump: JAL, JALR
• Upper Immediate: LUI, AUIPC
• System: ECALL, EBREAK, MRET, WFI (Hint, NOP)

RV32M Standard Extension

• Multiplication: MUL, MULH, MULHSU, MULHU
• Division: DIV, DIVU, REM, REMU

Other Extensions

• Zicsr: CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI
• Zifencei: FENCE.I (Instruction cache/pipeline flush)

CSR Registers

Machine-Mode CSRs

Read-Only CSRs

UART Subsystem

Integrated UART controller for communication and system control.

• System Programmer: Loads compiled programs (.hex) into Instruction Memory.
• Standard Output: MMIO-based character output; putchar/printf write characters to PRINT_ADDR, sent to host as RES_PRINT packets.
• Standard Input: MMIO-based character input; host sends bytes via CMD_INPUT, stored in INPUT_FIFO; getchar/scanf poll INPUT_ADDR until a byte is available.

Protocol Specification

1. Configuration

FIFO Sizes

2. Packet Structure

RX Packet (Host → FPGA)

• Payload: CMD_WRITE — Address (4B) + Data (nB), little-endian.
• Checksum: Sum of all bytes (START through last PAYLOAD byte), truncated to 8 bits.

TX Packet (FPGA → Host)

3. Commands (CMD)

4. Responses (RES)

5. Boot Sequence

1. Host sends CMD_RUN.
2. CPU begins execution and immediately sends RES_BOOT (hardware-generated via boot_flag).
3. Host enters CPU Console; keyboard input becomes active (line-buffered, sent as CMD_INPUT).
4. User program output follows as RES_PRINT packets; getchar()/scanf() in the program poll INPUT_ADDR.
5. On _exit(code), CPU sends RES_EXIT with the exit code.

Software & Tools

Note: The programmer tool is Windows-specific due to Win32 API usage (CreateFileA, ReadFile, WriteFile, etc.).

Directory Structure

Software/
├── runtime/        # Common bare-metal runtime (shared by all apps)
│   ├── crt0.S          # Startup code: sp init, BSS clear, main call, trap handler
│   ├── linker.ld       # Linker script: IMEM @ 0x0, DMEM @ 0x20000, stack @ 0x40000
│   ├── syscalls.c      # MMIO syscalls: putchar, printf, sprintf, _exit, memcpy, etc.
│   └── common.mk       # Shared Makefile rules (compile, link, hex generation)
├── apps/           # Application source code
│   ├── firmware/       # Custom test firmware
│   ├── coremark/       # CoreMark benchmark
│   ├── dhrystone/      # Dhrystone benchmark
│   └── riscv-tests/    # Official RISC-V test suite (submodule)
├── build/          # Compiled output (per-app subdirectories)
│   ├── firmware/       # firmware.hex, firmware.elf, *.o
│   ├── coremark/       # coremark.hex, coremark.elf, *.o
│   ├── dhrystone/      # dhrystone.hex, dhrystone.elf, *.o
│   └── riscv-tests/    # add.hex, lw.hex, mul.hex, ...
└── programmer/     # Host-side UART programming tool (Windows)

Toolchain Requirements

• Compiler: riscv-none-elf-gcc
• Architecture: rv32im_zicsr_zifencei
• ABI: ilp32
• Compiler Flags: -O2 -nostdlib -nostartfiles -ffreestanding

runtime/ — Common Bare-Metal Runtime

Shared startup and syscall code used by all applications.

Supported Functions

I/O

String & Memory

Timer

apps/firmware/ — Custom Test Firmware

A bare-metal test program written in C.

Files

Build

cd Software/apps/firmware
make clean && make

apps/coremark/ — CoreMark Benchmark

Runs the EEMBC CoreMark benchmark (v1.0) on bare-metal RISC-V.

Files

Build

cd Software/apps/coremark
make clean && make

CoreMark requires ≥ 10 seconds of continuous execution for a valid result. At 263.7 CoreMark/s, ITERATIONS=3000 gives ~11.4 seconds.

apps/dhrystone/ — Dhrystone Benchmark

Runs the classic Dhrystone 2.2 synthetic integer benchmark.

Files

Timer Mechanism

Dhrystone timing uses the mcycle hardware counter (100 MHz):

Start_Timer()  →  Begin_Time = (long)read_csr(mcycle);
Stop_Timer()   →  End_Time   = (long)read_csr(mcycle);

Build

cd Software/apps/dhrystone
make clean && make

apps/riscv-tests/ — Official RISC-V Test Suite

RISC-V ISA compliance tests (git submodule).

Build

cd Software/apps/riscv-tests
make TEST=add run

# Build all tests
make all-hex
# Output: Software/build/riscv-tests/*.hex

programmer/ — Host-Side UART Programming Tool

A Windows-only interactive command-line tool that communicates with the FPGA over UART.

Files

Menu

1. RESET    Reset System
2. BUILD    Build Program Image  (invokes make, optional immediate write)
3. WRITE    Write Program Image
4. RUN      Run Program & CPU Monitor
5. EXIT     End Program

On BUILD, after a successful make, the tool asks:

Write Program Now? (Y/N):

If Y, it immediately uploads the freshly built .hex without re-selecting the image.

Protocol Constants

Serial Port Settings

Build

cd Software/programmer
gcc programmer.c serial_port.c -o programmer.exe

Typical Workflow

cd Software/programmer
programmer.exe

1. Enter COM port number (e.g., 3 for COM3)
2. RESET — Halt and reset CPU
3. BUILD — Build selected app, then optionally write immediately
4. WRITE — Upload selected .hex to IMEM
5. RUN — Start CPU and enter CPU Monitor (press q to exit)

Simulation

Vivado Simulator

This project relies on Vivado Simulator (XSim) for functional verification.

1. Setup:

   • Add RTL/Testbench/cpu_testbench.sv to the project as a Simulation Source.
   • Set cpu_testbench as the Top Module in simulation settings.

2. Waveform:

   • Add Simulation/waveform.wcfg to the simulation sources for pre-configured signal views.
   • This configuration includes grouped signals for each pipeline stage (IF, ID, EX, MEM, WB) and debug interfaces.

3. Execution:

   • Run Behavioral Simulation.
   • The testbench prints [BOOT], [PASS], or [FAIL: exit=N] based on CPU events.

Directory Structure

• RTL/: Top-level FPGA module (riscv_cpu_fpga.sv)
  • Core/: SystemVerilog source code for the RISC-V CPU Core
  • UART/: Source code for the UART controller and PHY
  • Testbench/: Simulation testbench files
• Simulation/: Waveform configuration files for Vivado Simulator
• Software/: Firmware, benchmarks, and host programming tool
  • runtime/: Common bare-metal runtime (shared by all apps)
  • apps/: Application source code (firmware, coremark, dhrystone, riscv-tests)
  • build/: Compiled output per app
  • programmer/: Host-side UART programming tool (Windows)
• Constraints/: FPGA constraint files (.xdc)

License

See LICENSE file for details.

Contributors

Developed as part of a RISC-V CPU design project.