基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instruction set:single-cycle, multi-cycle, and a microsystem based on the multi-cycle cpu.

Single and Multi-cycle ARM processors implemented using VHDL

A multi-cycle CPU which supports 54 Mips instructions

OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

A Simple 8-bit Multi-Cycle CPU design and implementation using Logisim. Includes a custom datapath, ALU, and hardwired control logic.