The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Welcome to the ultimate list of resources for formal verification techniques and tools. This repository aims to provide an organized collection of high-quality resources to help professionals, researchers, and enthusiasts stay updated and advance their knowledge in the field.

CoreIR Symbolic Analyzer

This repo is created to include illustrative examples on object oriented design pattern in SV

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

A Coq framework to support structural design and proof of hardware cache-coherence protocols

Btor2 parser, circuit mitter, and code optimizer

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Generate, Simulate & Summarize Verilog Code with GenAI and Iverilog tool

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

SystemVerilog tutorial on how and why to use clocking blocks

FPGA implementation of a RISC-V RV32IMF softcore with IEEE-754 FPU and interrupt/CSR extensions, validated on Nexys A7.

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification.

Deterministic hardware architecture verification for robotics and embedded systems. Detects electrical compatibility and integration failures before PCB fabrication and firmware bring-up. CI-friendly with deterministic exit codes and structured reports.

RTL implementation of a 32-bit IEEE-754 single-precision floating-point multiplier in SystemVerilog, featuring SVA-based property checking

AES-128 co-simulation between SystemVerilog, C DPI, and Python for hardware verification.

Triple Modular Redundancy system with temporal monitor for hardware Trojan detection

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

4×4 7-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.

FIFO Verification Environment built with SystemVerilog, leveraging Object-Oriented Programming (OOP) for robust testbenches, including comprehensive Functional Coverage and SystemVerilog Assertions (SVA) for thorough design validation.

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

A multi-agent forensic audit engine for Infineon SmartRDI hardware code using LangGraph. Features an adversarial "Critic Layer" for hallucination-free bug detection, automated C++ remediation, and GTest generation.