donev-stan/SystemVerilog

FIFO Verification Environment built with SystemVerilog, leveraging Object-Oriented Programming (OOP) for robust testbenches, including comprehensive Functional Coverage and SystemVerilog Assertions (SVA) for thorough design validation.

assertions coverage digital-design fifo functional-coverage hardware-verification object-oriented-programming system-verilog testbench uvm verification verilog

SystemVerilog

A robust FIFO (First-In, First-Out) Verification Environment. It's built with SystemVerilog and leverages Object-Oriented Programming (OOP), Coverage, and Assertions to provide a comprehensive setup for verifying FIFO designs. The repository includes essential components such as assertions, FIFO and dual-port memory designs, interfaces, read and write agents, a scoreboard for data integrity, and transaction definitions.

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SystemVerilog83.3%Verilog16.7%

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Created February 15, 2022

Updated June 26, 2025

donev-stan/SystemVerilog | GitHunt

donev-stan/SystemVerilog

SystemVerilog

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