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Sidshx/anycore-riscv-src

The RTL source for AnyCore RISC-V

anycore

This contains the RTL for Anycore and associated simulation and synthesis framework for the latest RISCV based development of AnyCore

Languages

SystemVerilog97.8%Verilog2.2%

Contributors

ANMO
Other
Created April 3, 2022
Updated March 23, 2022
Sidshx/anycore-riscv-src | GitHunt