Repositories
24Image Resample using Bicubic Interpolation
Must-have verilog systemverilog modules
Advanced Architecture Labs with CVA6
BaseJump STL: A Standard Template Library for SystemVerilog
Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
No description provided.
No description provided.
RISC-V CPU Core
Lean but mean RISC-V system!
Let's write an OS which can run on RISC-V in Rust from scratch!
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
A List of Free and Open Source Hardware Verification Tools and Frameworks
GPGPU microprocessor architecture
lowRISC Style Guides
Berkeley's Spatial Array Generator
Repository to host and maintain scale-sim-v2 code
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
Spike, a RISC-V ISA Simulator
Google AI 2018 BERT pytorch implementation
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core