Samuel A. Falvo II
sam-falvo
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C
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An open source Video Display Controller following in the footsteps, but not a clone, of the Commodore 8568 VDC chip.
Generic Component Object Model, a clean-room reimplementation of Component Object Model (in-process only).
From Bitbucket -- A blog engine in Forth.
Archive of Dr. Martin Richards' BCPL, MCPL, and Cintpos (a subset of Tripos)
Project Norebo
Repositories
75My Logic Analyzer. A logic analyzer using an FPGA's block RAMs for storage.
From Bitbucket -- A blog engine in Forth.
An open source Video Display Controller following in the footsteps, but not a clone, of the Commodore 8568 VDC chip.
Archive of Dr. Martin Richards' BCPL, MCPL, and Cintpos (a subset of Tripos)
No description provided.
Modern C64 Forth
Digital Research GEM version 3.3
Virtual Processor 64 (VP64) is an emulator or virtual machine with the same instruction set as the eP64 (Embedded Processor 64-bit) powering the Kestrel-3. VP64 is expected to be quite useful in writing and validating software for the Kestrel-3 without requiring a complete set of physical hardware resources.
Sources for 2013 Oberon System.
Project Norebo
Generic Component Object Model, a clean-room reimplementation of Component Object Model (in-process only).
All CPU and MCU documentation in one place
No description provided.
The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
No description provided.
Unable to poll for changes to data, I need a POC to submit a bug report to requests team. This is that POC.
An adaptation of IEEE-1355 DS-SE-02 serial I/O for use with the Kestrel-3 for standardized I/O channels.
Jon Bentley's DFORMAT troff preprocessor, reconstituted.
6502/65816 cross assembler
Miscellaneous tools and scripts involving the RC2014 in some way.
Documentation for the RISC-V Supervisor Binary Interface
Software Survivalist
I'm tired of having to hunt down how to build Yosys and friends every time. Time to script this stuff once and for all.
Generate Moore/Mealy/Hybrid state machine decoder logic in Verilog.
Python Console User Interface Library
A port of my video game, Equilibrium, to Common Lisp and SDL2.
My completely pathetic set of dotfiles which I like to share between machines. Yeah, I know, I'm a loser.
No description provided.
No description provided.
Automatic test-case design, implementation, and coverage management tool, inspired by the Cleanroom Software Engineering design process requirements. (Experimental)