Martin Povišer
povik
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Top Repositories
Repositories
44SystemVerilog frontend for Yosys
No description provided.
FPGA design for a basic logic analyzer
No description provided.
No description provided.
high abstraction synthesis
No description provided.
toy technology mapper
No description provided.
Proposal for cutout creation with OpenSTA
OpenSTA engine (fork of OpenROAD's fork)
No description provided.
SystemVerilog compiler and language services
End-to-end synthesis and P&R toolchain
No description provided.
Multi-platform nightly builds of open source digital design and verification tools
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Press Mold Mapper: OpenSTA-based standard cell mapper
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
ABC: System for Sequential Logic Synthesis and Formal Verification
Test suite designed to check compliance with the SystemVerilog standard.
sample design for demonstation of Fold features
fork of Yosys for Fold CI, see https://github.com/YosysHQ/yosys for upstream
Nix Packages collection
Description of Apple's LEAP ISA
A bootloader and experimentation playground for Apple Silicon
Linux kernel source tree
No description provided.
QuickLogic's plugins for Yosys (fork of F4PGA plugins)