Repositories
41Nix derivations for EDA tools
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
The next generation of OpenLane, rewritten from scratch with a modular architecture
No description provided.
A user project example for caravel that uses https://github.com/secworks/aes
This repository is the GF180MCU port of management core for Caravel. For more information about the Caravel management SoC, see https://github.com/efabless/caravel_mgmt_soc_litex.
Extra backend checks for sky130
An Open-source FPGA IP Generator
Pre-hardened DFFRAM macros using DFFRAM
Antlr4-based parser for the input files to OpenLane custom IO placers.
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Skywaters 130nm Klayout PDK
Example digital project for the Efabless Caravel "openframe" harness
No description provided.
No description provided.
The Panamax 130-pin padframe for SkyWater sky130
Example digital project for the Efabless Caravel "openframe" harness
No description provided.
No description provided.
Open-source IPs Package Manager (IPM)
https://caravel-user-project.readthedocs.io
No description provided.
No description provided.
The analog signal processing and timing frontend subsystems for the Frigate harness chip
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
AUC Open Hardware Lab (AUCOHL) IP Utilities
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
No description provided.
Multi-Project Support for Caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.