Klessydra
klessydra
A family of processing cores and accelerators developed at the Digital Systems Lab at Sapienza University of Rome, Italy
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Repos
22
Stars
159
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47
Top Language
VHDL
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An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance
An open-source microcontroller system based on RISC-V
A morphing processor capable of changing its architecture depending on the active number of harts
Repositories
22Optimized primitive digital building blocks used across multiple different modules
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
An open-source microcontroller system based on RISC-V
A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
This app is a floating point calculator for custom defined floats. It can do arithmetic operations, and conversions on any defined float with a custom defined exponent, mantissa, and bias.
Spike, a RISC-V ISA Simulator with added 8-bit vector floating point support
Hyperdimensional Copressing Unit (HDCU), a highly flexible and reconfigurable hardware accelerator designed for optimizing the performance of machine learning tasks.
Highly Parametrizable Vector Coprocessor Unit for Klessydra Cores, with Scratchpad Memories
No description provided.
A Fault Tolerant Implementation of the Klesydra-T13x core, which uses IMT to achieve temporal and partially-spatial redundancy.
A morphing processor capable of changing its architecture depending on the active number of harts
No description provided.
Klessydra Specific Libraries used by the software suite in Klessydra
2D Convolution Using VHDL
A collection of software programs in C and C++ made to target Klessydra.
No description provided.
A highly Out-of-Order execution processor for the Klessydra family
No description provided.
No description provided.
Single-Core Single-Thread four pipeline stage in-order execution processor with custom vector accelerator