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akira2963753
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This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.
32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.
This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.
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This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.
This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.
32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.
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