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Python Productivity for ZYNQ
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
Vitis In-Depth Tutorials
Brevitas: neural network quantization in PyTorch
Xilinx Embedded Software (embeddedsw) Development
Dataflow compiler for QNN inference on FPGAs
Repositories
439Xilinx Embedded Software (embeddedsw) Development
Fork of LLVM to support AMD AIEngine processors
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
QEMU libsystemctlm-soc co-simulation demos.
The Torch-MLIR project aims to provide first class support from the PyTorch ecosystem to the MLIR ecosystem.
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
AMD OpenNIC Project Overview
Representation and Reference Lowering of ONNX Models in MLIR Compiler Infrastructure
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Repo Manifests for the Yocto Project Build System
An MLIR-based toolchain for AMD AI Engine-enabled devices.
FPL'26 Optimization Contest
Xilinx QDMA IP Drivers
Run Time for AIE and FPGA based platforms
No description provided.
Brevitas: neural network quantization in PyTorch
The official Xilinx u-boot repository
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Introductory examples for using PYNQ with Alveo
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
No description provided.
SystemC/TLM-2.0 Co-simulation framework
Alveo Versal Example Design
Dataflow compiler for QNN inference on FPGAs
Python Productivity for ZYNQ
No description provided.
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Vitis In-Depth Tutorials