Shubham Upadhyay

Portfolio / Personal Repo

RISC-V RV32I processor implemented in Verilog, featuring both a Single-Cycle core and a fully modular 5-stage Pipelined core with hazard detection, forwarding, and synthesis support using Yosys.

Morphological image filtering system on PYNQ-Z2 FPGA implementing min, max, and median filters. Demonstrates HW/SW co-design with VHDL acceleration and Python orchestration for real-time image enhancement

5-bit Galois Linear Feedback Shift Register for pseudo-random sequence generation. Implements maximal-length sequence (31 states) suitable for cryptographic applications, BIST mechanisms, and data scrambling with comprehensive waveform verification.

A complete 1×3 NoC router implemented from RTL to GDSII using the Sky130A PDK. Includes full functional verification, synthesis (Yosys), and physical design using OpenLane/OpenROAD, culminating in a signoff-clean GDS layout.

A round-robin arbiter implemented in Verilog. The design resolves simultaneous requests using a rotating priority scheme to ensure fair access among all requesters.

Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.

Parameterized synchronous FIFO buffer implementation in Verilog with pointer-based read/write operations, full/empty flags, and comprehensive testbenches using waveform analysis and gate-level schematic verification. Includes detailed functional verification through simulation testbenches and assertion-based checks to ensure data integrity.

Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling trade-offs with complete hardware implementation.

Creative Moore FSM representing personal life milestones from undergrad to VLSI career aspirations. Fun educational project demonstrating state machine concepts through storytelling, complete with synthesis results and waveform analysis. Combines digital design with personal narrative.

A Python-based sorting algorithm visualizer that demonstrates Bubble, Quick, Merge, and Radix Sort with step-by-step animations using Matplotlib. Includes performance comparison, command-line customization, and side-by-side algorithm insights.

Fully parameterized UART (Universal Asynchronous Receiver Transmitter) module in Verilog with FSM-based transmitter and receiver, configurable baud rate generator, and support for full-duplex communication. Includes 16x oversampling for accurate bit sampling and loopback testbench for simulation.

Comprehensive collection of modular, synthesizable Verilog circuits including combinational logic (multiplexers, subtractors, comparators) and sequential designs (shift registers, counters, timers). Organized library with testbenches, waveforms, and synthesis reports for rapid prototyping and design reuse.

SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.

Sensor-aware 4-road traffic light controller using Finite State Machine in Verilog. Dynamically manages traffic flow with priority-based signal allocation, timer-controlled phase transitions, and real-time traffic monitoring for smart city applications.

Binary pattern "1011" detector implemented using both Mealy and Moore FSM architectures. Comparative analysis of output timing, state usage, and architectural trade-offs with detailed waveform analysis and synthesis results.

High-speed 8×8 Dadda multiplier designed in 45nm CMOS technology with hybrid transmission gate/CMOS logic. Features 4:2 compressor-based partial product reduction, critical path delay of 0.204ns, and comprehensive delay & power analysis.

High-performance 8-bit Manchester adder optimized for accumulator applications using hybrid CMOS/PTL logic. Features transmission gate carry chain, post-layout power analysis, and comprehensive comparison with other adder architectures.