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A complete computer science study plan to become a software engineer.
ECE 4750 Tutorial 3: PyMTL Hardware Modeling Framework
https://caravel-user-project.readthedocs.io for Grapevine EE 372
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
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ECE 4750 Tutorial 3: PyMTL Hardware Modeling Framework
https://caravel-user-project.readthedocs.io for Grapevine EE 372
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
ECE 4750 Tutorial 2: Git Distributed Version Control System
ECE 3140: Embedded Systems. Project on Locks and Concurrency.
Final Project for ECE 3140 (Embedded Systems): Model Rocket Flight Computer and Launch Simulator
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Keep track of internships for Summer 2020 for undergraduates interested in tech./SWE/related fields
A complete computer science study plan to become a software engineer.
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iOS portion of the hack_challenge
App for organizing goals and viewing progress
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