Marek Pikuła
MarekPikula
FPGA developer by day, DevOps engineer by night.
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90
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16
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Python
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Top Repositories
Automatically generated Python Headscale API
Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
Export Python description from the systemrdl-compiler register model
Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.
Matter (formerly Project CHIP) creates more connections between more objects, simplifying development for manufacturers and increasing compatibility for consumers, guided by the Connectivity Standards Alliance.
Marek Pikuła – a personal blog
Repositories
90Matter (formerly Project CHIP) creates more connections between more objects, simplifying development for manufacturers and increasing compatibility for consumers, guided by the Connectivity Standards Alliance.
Marek Pikuła – a personal blog
Slides and resources from conferences.
Export Python description from the systemrdl-compiler register model
Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.
Monorepo menagerie of container images and associated build automation (from containers namespace)
Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
(Mirror) Development environment useful for debugging RVV (RISC-V Vector) software without hardware with GDB.
No description provided.
Resources for RISC-V Summit Europe 2025 with topic: Enabling RISC-V CI in Open-Source Projects: Challenges and Solutions
Build your hardware, easily!
flask extension for integration with the awesome pydantic package
Modern audio compression for the internet.
Mirror of https://git.jakstys.lt/motiejus/undocker
Automatically generated Python Headscale API
Generate code coverage reports with gcc/gcov
Finka is the VexRiscv based SoC in Blackwire responsible for WireGuard session management
SpinalHDL components for Corundum Ethernet
Blackwire SpinalHDL components implementing WireGuard primitives
Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path
BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
ChaCha20-Poly1305 AEAD in VHDL
Blackwire overview, status, roadmap and top-level documentation.
Chaos Assistant TODO app for chaotic project management
The Meson Build System
:earth_africa: `debian-debootstrap` Docker image for multiple architectures
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)