Keerthi Patil

KeerthiPatil-RTL

Digital hardware design and verification focused on RTL development, CMOS VLSI (45nm), RISC CPU implementation, and embedded firmware development.

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Verilog50%SystemVerilog25%Python25%

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Verilog

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STM32-NUCLEOF411-RE

STM32 NUCLEO-F411RE embedded firmware projects emphasizing register-level control, interrupts, and peripheral interfacing, highlighting hardware–software interaction, systematic debugging, and hands-on microcontroller development.

1Python

Cadence-veri-RISC-CPU-VERILOG

1Verilog

Cadence-Virtuoso-Projects

Cadence Virtuoso | 45nm CMOS | VLSI Design | CPU/ALU

RTL-designs

1Verilog

rv32i-single-cycle-processor-systemverilog

0SystemVerilog

Repositories

KeerthiPatil-RTL/rv32i-single-cycle-processor-systemverilog

No description provided.

SystemVerilog00Updated 1 month ago

KeerthiPatil-RTL/STM32-NUCLEOF411-RE

Python10Updated 2 months ago

KeerthiPatil-RTL/Cadence-veri-RISC-CPU-VERILOG

No description provided.

Verilog10Updated 3 months ago

KeerthiPatil-RTL/Cadence-Virtuoso-Projects

Cadence Virtuoso | 45nm CMOS | VLSI Design | CPU/ALU

10Updated 2 months ago

aluasiccadence-virtuosocmos-45nmcpudigital-designlayoutsrtlverificationvlsi

KeerthiPatil-RTL/RTL-designs

No description provided.

Verilog10Updated 2 months ago

Keerthi Patil

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