Kastner Research Group

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Documentation for CSE 160

A plugin backend for hls4ml targeting AMD AI Engines (AIE)

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

The RIFFA development repository

No description provided.

Gate-level simulator for efficient hardware-software co-design.

No description provided.

Contains FPGA benchmarks for Vivado HLS and Catapult HLS

No description provided.

YosysHQ SVA AXI Properties

Bus bridges and other odds and ends

The public repo of the AKER framework for safe and secure SoC access control systems

Projects and Labs for the Parallel Programming for FPGAs book

Pre-Silicon Hardware Fuzzing Toolkit

Waiter configurations

Machine learning on FPGAs using HLS

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

fabricant.ucsd.edu configuration

Fuzzer instrumentation for Verilog Fuzzing. Adds various coverage metrics, including Taint.

No description provided.

No description provided.

Fuzzing for SpinalHDL

FUSS: fuzzing on a shoestring

A Modular Open-Source Hardware Fuzzing Framework

rfuzz: coverage-directed fuzzing for RTL research platform

This is the source code of our submission "Bridging the Gap between Hardware Fuzzing and Industrial Verification" for GLSVLSI 2025.

Fuzzing General-Purpose Hardware Designs with Software Fuzzers

Project Repo for the Simulator Independent Coverage Research