Aruna Jayasena

Surface Duo Dual Experience ( 🍰 AOSP | Android 16 | DUO1 | DUO2 )

GitHub Mirror of Intel BE200 Wifi Module Linux Firmware

Using stereo vision 👀 to identify the obstacles by processing images on a FPGA

Realtime depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

Artifacts of our TFHE Processing Unit

Camaro6 CAD files

Integration of two camera 📷 modules to Basys 3 FPGA

hello world ! 🌎

No description provided.

3D model of the Final drone assembly for the Simulation

Hardware-Parametric Scheduling for TFHE Accelerators

Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.

Peripheral library 📚 for open source FPGAs based on iCE40. (Configured for ICESugar-Nano)

Verilog implementation of RSA 4096

sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

No description provided.

PIPE based open-source simulation model for Xilinx PICE IP

An app which will do various stuff for DUO-DE ROM

🚨 Cryptographic Leakage evaluation on Hardware

Design a sequential circuit (FSM) and implement using Verilog

A compiler for homomorphic encryption

A simple microprocessor (hence, called a nanoprocessor) created using ISE design suite capable of executing a simple set of instructions.

Alpha trimmed mean filter and Adaptive filter implemented using Scilab

Stopwatch ⏱️ implemented using Verilog with Vivado

Multiprocessor Network on Chip which consists of 4 Mork1x processors

Assertion based Network on Chip Security Implementation

Verilog variables descriptions to graphs converting tool

No description provided.

Flatten RTL hierarchy designs with Yosys

No description provided.