open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Documenting the Xilinx 7-series bit-stream format.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

Xilinx Virtual Cable Server for Raspberry Pi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

Minimal DVI / HDMI Framebuffer

Plugins for Yosys developed as part of the F4PGA project.

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Project X-Ray Database: XC7 Series

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:

Re-coded Xilinx primitives for Verilator use

building blocks for accelerating ZK proofs over binary fields

Open-source CSI-2 receiver for Xilinx UltraScale parts

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.

Verilog Implementation of Run Length Encoding for RGB Image Compression

This repository contains all labs done as a part of the Embedded Logic and Design course.

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

A library of VHDL components for Neural Networks

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure access to commercial and private IoT clouds, real-time monitoring, secure boot, and remote firmware updates. The built-in Trusted Execution Environment provides hardware-enforced separation ...

Innervator: Hardware Acceleration for Neural Networks

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。