Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Customized UVM Report Server

Read-only mirror of https://gitlab.com/tymonx/pytcl

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

UVM-Based Verification Project for a YAPP (Yet Another Packet Protocol) Router

This project implements a digital clock with alarm functionality in Verilog and SystemVerilog.