A High-performance Timing Analysis Tool for VLSI Systems

Standard Cell Library based Memory Compiler using FF/Latch cells

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

A Standalone Structural Verilog Parser

VLSI EDA Global Router

Library of approximate arithmetic circuits

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Electrical And Electronic Engineering Course Materials

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

All the projects and assignments done as part of VLSI course.

genetic algorithm usage for routing optimization ( pyqt )

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect tradeoff between the contradictory objective functions in CMOS RO optimal design. This tool is applied for intelligent estimation of the circuit parameters (channel width of transistors), which have a decisive influence on RO specifications. Along the optimal RO design in an specified range of oscillaton frequency, the Power Consumption, Phase Noise, Figure of Merit (FoM), Integration Index, Design Cycle Time are considered as objective functions. Also, in generation of Pareto front some important issues, i.e. Overall Nondominated Vector Generation (ONVG), and Spacing (S) are considered for more effectiveness of the obtained feasible solutions in application. Four optimization algorithms called Multi-Objective Genetic Algorithm (MOGA), Multi-Objective Inclined Planes system Optimization (MOIPO), Multi-Objective Particle Swarm Optimization (MOPSO) and Multi-Objective Modified Inclined Planes System Optimization (MOMIPO) are utilized for 0.18-mm CMOS technology with supply voltage of 1-V. Baesd on our extensive simulations and experimental results MOMIPO outperforms the best performance among other multi-objective algorithms in presented RO designing tool.

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

VLSI Physical Design

Some ramblings about my major. 一些有关我的专业的碎碎念

delay estimation, sequencing, power dissipation of digital circuits

Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.

Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

FuzzyIWO-Algorithm (Adaptive fuzzy optimisation algorithm)

No description provided.

Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.

Approximate multipliers of 8bit and 16bit

⚙️ Explore Cadence Virtuoso projects showcasing 45nm CMOS technology in VLSI design, including an 8-bit CPU/ALU and critical circuit analysis.

No description provided.

No description provided.