A complete open-source design-for-testing (DFT) Solution

🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit

ACT hardware description language and core tools.

DATC RDF

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

Converts GDSII (IC layout database) files to SVG (Vector graphics) files.

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

grayscale conversion system and simple convolution system

Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

🕹 OpenPARF-MLCAD2023: A Multi-Electrostatics Based FPGA Macro Placer Considering Cascaded Macros Groups and Fence Regions (MLCAD'23 Contest Submission)

A library for fast and optimized VLSI Computer-Aided-Design algorithms

Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI

A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

RTL to GDSII implementation of a Mealy FSM-based ASIC Toll Booth Controller

This project demonstrates the complete design, layout, simulation, and verification of a **CMOS Inverter** using the **Electric VLSI Design Tool**.

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

GELSA, a Performance Driven Flexible Placement Tool for Analog Integrated Circuits.

Electric VLSI is a powerful open-source EDA tool for VLSI layout and schematic design, written in Java. Here is the step by step installation guide.

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

This repository implements technology mapping using minimum cost tree-covering.

This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

EC704 - VLSI Design Automation

This repo implements VLSI static timing analysis using C++.

Course projects for Physical Design for Nanometer ICs (Fall 2023), NCKUEE Graduate School.