Verilog Generator of Neural Net Digit Detector for FPGA

a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.

A library to generate parameterized Verilog code from C++. Allows you to assemble Verilog modules in C++, use C++ syntax to dynamically generate complex connections, parameterize code, and ultimately get the Verilog code automatically generated.

Compiler for State Automata - tool for compiling Deterministic Finite Automata to machine code.