Various HDL (Verilog) IP Cores

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

A configurable C++ generator of pipelined Verilog FFT cores

IceChips is a library of all common discrete logic devices in Verilog

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

An 8 input interrupt controller written in Verilog.

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

A wishbone controlled FM transmitter hack

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

Practices related to the fundamental level of the programming language Verilog.

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

A coocbook of HDL (primarily Verilog) modules

University of Marmara, CSE3015 2018 Fall Project

Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.

No description provided.

数电作业

Basics of Verilog implementation

Verilog modules for reference

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Solutions for 100+ questions in HDLBits using verilog

A collection of digital circuits using Verilog.

A Verilog HDL code