RTL data structure

Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

No description provided.

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

Getting started with SystemVerilog: Hardware Description Language for design and verification.

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

An FPGA implementation of Cummings' Asynchronous FIFO

Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u

A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

This collection of verification diagrams is created to help educators, students, and engineers visualize complex hardware verification concepts. These illustrations transform complex concepts into understandable visuals.

Example of DPI-C usage in UVM with Vivado simulator (xsim) and Altair (Metrics) DSim

This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.

1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage fo

Reusable and scalable verification framework for Deep Neural Network (DNN) accelerators using Pyuvm, Cocotb, and Portable Stimulus Standard (PSS). Supports generic layer-wise verification and automated multi-layer scenario generation.

A synthesizable Gigabit Ethernet MAC IP core with full UVM verification environment.

Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).

Examples to apply UVM to existing module based test benches at ease

in this repo will continue with rtl codes for implementation and verification of the designing, and 100 percentage of coverage model. various design using system verilog in questa and vcs and digital compiler.

This Repository contains the Universal Verification Methodology (UVM) verification of a Synchronous FIFO design

SystemVerilog tutorial on how and why to use clocking blocks

Uvod u UVM verifikaciju, prepravljena hijerarhija i prekucani kodovi sa youtube snimka, osnovne akademske studije

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage for the RTL verification sign-off. Skills

Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.

Verification of D-FF using UVM on EDA playground