UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions

UVM-based verification environment for an APB FIFO design with comprehensive test coverage and bug analysis.

UVM-based register verification environment using explicit predictor

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Low-Power CGRA Design Methodology (WIP)

Updated as I learn more about UVM