OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

🟢 super fast 🚀 tiny 🐥 𝘾 printf-look-and-feel ✍ trace code, in ⚡ interrupts ⚡ too ‼️, and real-time PC 💻 logging 👀

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption

This is a tutorial on standard digital design flow

This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.

Gate-level timing estimation toolkit

A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

Evaluation Framework for Self-Suspending Task Systems

GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.

Compiler backend from packing to bitstream generation.

Static Timing Analyser (LIP6)

Detect side channels with statistically rigorous methods.

SerDes RTL design, verification using UVM and Physical design.

Academic-grade Worst-Case Execution Time analysis using LLVM infrastructure for embedded systems and real-time applications

ttcp is a simple Rust-coded tool to measure TCP timing and detect anomalies.

Analysis of radio pulsar parameters and their relationships with nulling statistics

GG はシリアルコンソールを実現するための支援ライブラリです。コンソールを組み込むための補助的なツール（例えば書式付出力や文字列変換）を含みます。 GG for CCRX は ルネサス RX でのポーティング例です。

RTAS 2021 - Artifact Evaluation for "Timing Analysis of Asynchronized Distributed Cause-Effect Chains"

A side-channel analysis project implementing a Prime+Probe cache attack to recover AES encryption keys by analyzing first-round T-table accesses. Includes parallelized data processing, statistical analysis, and heatmap visualization.

This is a collection of scripts that is used to time DNS queries using BIND, and create DNS access traces with hit and miss times (cache hit and miss that is)

Implements a Mealy FSM that computes the 2’s complement of a serial binary input, showcasing the full hardware design workflow from logic to gate-level simulation.

Implementation of various sorting algorithms | python3

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

⏰ Fpga Multi Clock Synchronization

Please check out the attached link.

ML-powered platform that analyzes Verilog RTL circuits and predicts timing violations early using structural feature extraction and a Decision Tree model.

PHPUnit extension to track and report test execution times.