Build your hardware, easily!

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

RISC-V XV6/Linux SoC, marchID: 0x2b

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

RISC-V microcontroller IP core for embedded, FPGA and ASIC applications

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Basic RISC-V Test SoC

Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

The Antikernel operating system project

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

System on Chip toolkit for Amaranth HDL

ElemRV - End-to-end Open-Source RISC-V Microcontroller

A Modeling and Verification Platform for SoCs using ILAs

Development platform for the Espressif ESP32 WiFi/Microcontroller SoC

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

An open-source 32-bit RISC-V soft-core processor

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

CMake based hardware build system

Chisel implementation of Neural Processing Unit for System on the Chip

Template project for LiteX-based SoCs

Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.

A ZipCPU SoC for the Nexys Video board supporting video functionality

Zucker SOC

System-on-Chip Resource Adaptive Scheduling using Deep Reinforcement Learning

Senior Design