[WIP] Dockerize Synopsys/Cadence EDA tools

This is a tutorial on standard digital design flow

embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC

There is segmentation fault of VCS which should be fixed.

Customized UVM Report Server

Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

:book: Mastering FPGASIC Book

A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.

Example of a full DC synthesis script for a simple design

Technology file parser in Rust

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

:star2: Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown

Exploring Synopsys(R) synthesis tools

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

Typical project for Synopsys DC Compiler

I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

iDoka's web page on Github

Implementation of a MIPS CPU using Verilog.

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

Command completion for Synopsys (Black Duck) Detect commands

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

Master degree project for Synthesis and Optimization of Digital Systems

A small collection of tutorials and tools for ASIC design.

Verilog practice sessions by Mr. Sujit Panda

Waveform viewer for Synopsys CustomCompiler, text table format, simulation data

Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

2AMD15 - Big Data Management - Prof. Papapetrou - TU/e

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