An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

32-bit Superscalar RISC-V CPU

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

DUTH RISC-V Superscalar Microprocessor

A compiler, assembler, and processor.

Super scalar Processor design

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

Superscalar dual-issue RISC-V processor

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang

Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc

Superscalar OoO RISCV processor written in Chisel

Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture

A superscalar processor in Python

This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.

Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.

This repository includes Verilog and VHDL implementations of out-of-order and in-order superscalar processors, featuring reservation stations, pipelines, scoreboarding, and register files to explore instruction-level parallelism and hazard handling.

An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.

A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.

Out of order superscalar processor simulated in Javascript

RISCV Out-Of-Order CPU Core

Superscalar RV32IM Core

MCP server for SuperScalar — Bitcoin Lightning channel factories. Query protocol specs, estimate UTXO savings, and explore factory architectures.

CS-470 Homework 1