AMD OpenNIC Project Overview

Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]

AMD OpenNIC Shell includes the HDL source files

DPU-Powered File System Virtualization over virtio-fs

AMD OpenNIC driver includes the Linux kernel driver

Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism

[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference

LeapIO: Efficient and Portable Virtual NVMe Storage on ARM SoCs (ASPLOS'20)

DPDK Drivers for AMD OpenNIC

A research shell for Alveo V80

Alkali is a MLIR-based compiler infrastructure for SmartNICs. It allows developers to write target-independent programs, with the compiler automatically managing cross-NIC porting and performance optimization.

Dataflow-driven data packet processing on Agilio CX SmartNIC 2x10Gbe, aimed at low latency.

[Long Term Support] [SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference

Offloading DOCA-based Adaptive Routing onto NVIDIA BlueField-2 DPU. (卸载基于DOCA的自适应路由到NVIDIA BlueField-2 DPU上)

Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"

SmartTLS is the project introduced at the paper "A Case for SmartNIC-accelerated Private Communication" (APNET 20). It accelerates web servers by offloading TLS handshake protocol into network card (NIC).

基于 DPDK 和智能网卡的流量卸载试验. A flow offloading prototype base on DPDK and Mellanox/Nvidia SmartNIC.

Vitis Netwarking P4 Framework (VNP4 Framework)

Repo exploring hardware timestamping

Exploring eBPF Capabilities with Hardware Acceleration on FPGAs for High-Performance Networking

Netronome NIC applications with P4 and Micro-C

Programs and scripts to test TSN on Linux and Netronome Agilio SmartNIC

BlueField DPU Emulator - Development, testing, and CI/CD without physical hardware

Example to integrate Netronome SmartNICs with userspace driver

Programmable Transport Protocols that are deployed on hardware for extremely low latency in data centers.

Interference-aware CPU scheduling that enables performance isolation and high CPU utilization for datacenter server

SmartNICs & DPUs — programmable network/data‑plane accelerators: architecture, programming models (P4, eBPF/XDP), code examples, and performance examples.

No description provided.

userspace ixgbe driver for latency based on CPU cycles