RISC-V CPU Core (RV32IM)

A self-hosting and educational C optimizing compiler

32-bit Superscalar RISC-V CPU

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

RISC-V microcontroller IP core for embedded, FPGA and ASIC applications

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

RISC-V CPU Labs in Chisel

RISC-V Nox core

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A Single Cycle Risc-V 32 bit CPU

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

RISC-V RV32I[MA] emulator with ELF support

An open-source 32-bit RISC-V soft-core processor

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

Free RISC-V simulator and IDE for learning assembly — RV32IMF, step-by-step debugger and cache simulator

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

RISC-V RV32I CPU core

RISCV CPU implementation in SystemVerilog

伴伴學 RISC-V RV32I Architecture CPU

**RISC**uinho - A scratch in the possibilities in the universe of microcontrollers

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

An example in bare metal RV32 assembly for the longan nano board

RV32I single cycle simulation on open-source software Logisim.

Minimalistic RV32I RISC-V Processor in System Verilog