RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

F# RISC-V Instruction Set formal specification

Verilog implementation of multi-stage 32-bit RISC-V processor

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Open source ISS and logic RISC-V 32 bit project

Simple single cycle RISC processor written in Verilog

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

9444 RISC-V 64IMA CPU and related tools and peripherals.

A RISC-V virtual processor, written in Rust.

A Verilog RTL model of a simple 8-bit RISC processor

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

DUTH RISC V Microprocessor for High Level Synthesis

A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

An 8-bit RISC based processor designed in verilog with x86 instructions.

A tiny 8 bit RISC ISA for on-chip/on-FPGA management purposes

The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

A C++ pipeline based simulator of RSIC architecture.

Implementation of a 24 bit RISC processor

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

𝗖𝗼𝗺𝗽𝘂𝘁𝗲𝗿 𝗢𝗿𝗴𝗮𝗻𝗶𝘇𝗮𝘁𝗶𝗼𝗻 & 𝗔𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁𝘂𝗿𝗲 | 𝗖𝗦𝟯𝟵𝟬𝟬𝟭

A real time Microprocessor impemented in verilog and tested on Xilinx Artix FPGA.

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

RISC-V five stage pipline CPU

Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

Deluxe RISC processor

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

SISA Architecture Emulator

Procesador RISC segmentado creado con Proteus con Unidad de control, 5 segmentos, corrección de errores mediante unidad de detección de conflictos (DC) y ALU.