All the projects and assignments done as part of VLSI course.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

explore different implementations of adders and study their characteristics.

work done as part of VLSI Design practice course

Digital System Design Lab Codes using Verilog

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Progetto di Elettronica Digitale AA 2022-2023

My VHDL Codes during EE214 (Digital Lab) Spring 2020-21

Useful VHDL scripts for hardware description.

Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.

Digital Circuits: Ripple Carry Adder.

All the various adders in Verilog!

A repository for some modules I made while learning Verilog

Implementation of four Ripple-Carry Quantum Adders with Qiskit.

A 4-bit ripple-carry adder-subtractor created in Logisim.

Design and Verification of a complete multi-digit BCD adder, using both ripple-carry and carry look-ahead architectures. Design relied on modularity and hierarchy, while validation was implemented through behavioral reference model.

Vivado VHDL

N-bit adder implementations (Ripple Carry, Carry Lookahead, and Prefix) with synthesis using Cadence Genus. Area, power, and delay comparisons are provided for N = 4, 8, 16, 32, and 64.

This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

3-bit ripple carry adder implemented using discrete NMOS transistors and NAND gate logic without using any digital ICs.

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

No description provided.

designed simple digital circuits using verilog

Transistor-level design and transient simulation of a 4-bit Ripple Carry Adder using CMOS logic in Cadence Virtuoso (90 nm GPDK).

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.