📑 Neovim plugin to preview the contents of the registers

SystemRDL 2.0 language compiler front-end

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Control and status register code generator toolchain

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

q - vim like macro registers for your bash and zsh shell!

C++ templates for type-safe bit manipulation

Generate address space documentation HTML from compiled SystemRDL input

Generate UVM register model from compiled SystemRDL input

Vision Transformers Needs Registers. And Gated MLPs. And +20M params. Tiny modality gap ensues!

A Mewtocol protocol library to interface with Panasonic PLCs over TCP/Serial written in C#

A bunch of architectural headers for i386 and AMD64

[closed]🔥 virtual machine & assembler-style language 🔥

Modern Hardware/Software Interface (HSI) Documentation

Plugin to automatically load routes from a specified path and optionally limit loaded file names by a regular expression.

RISC-V CSR Access Routines

Julia Bit Manipulation Functions

HiSilicon ip camera SoCs SystemRDL registers description

NRF24L01+ (and clones) registers at your fingertips

List the current content of registers

Materials for the Computer Science course, Digital Design (Logic Circuits)

The Registers Specification

Generate boilerplate code of C macro definition for all registers and their fields of a chip.

Common parameter values for AMWA NMOS Specifications

Arduino example sketches demonstrating ADC Single Conversion, ADC in Free Running mode, ADC with Noise Reduction, ADC with Frequency tuning, PWM in Fast mode, Other PWM modes, 16bit Timer1 example, and a Watchdog example using an interrupt and/or system reset.

Registers are distributed, versioned lists of structured data. The Open Registers Compendium (orc) provides libraries and tools for reading, writing and manipulating data Registers.

Registers reference implementation

A Minimal STARK based zkVM.

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

HiSilicon SoC`s U-Boot initial register table parser into human readable format