Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Physical Design Flow from RTL to GDS using Opensource tools.

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

No description provided.

A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)

c compiler beluga with riscv32 backend

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

Frequency counter using a GPS receiver PPS output as its reference

C examples for picorv32 CPU

Xilinx FPGA loader

Physical design flow of the PicoRV32 processor using Cadence Genus and Innovus

Simple implementation of SOC around PicoRV32 soft core.

Softcore microcontroller with peripherals based on PicoRV32

SoC of PicoRV32i

Wrapper module for the PicoSoC to support the Digilent Basys 3

Complete RTL-to-GDSII implementation of the PicoRV32 RISC-V core using Cadence Xcelium, Genus, Innovus and Tempus (180nm) with 100MHz timing closure.

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

No description provided.

Logic Synthesis QOR study, the best and worst case for hold and setup

Files regarding synthesis and floorplanning of a RISC V proccessor, using Cadence Genus and Innovus. Project is part of class Digital VLSI-ASIC Design, 9th semester, ECE Aristotle University.