:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Ada-language framework

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

Rust support for the open-source NEORV32 RISC-V microcontroller.

🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

NEORV32 and a generic FAT file system called FatFs.

Delivrables and code base from a CentraleSupéléc project

[TFM] This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.