🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

Minimalist 8 bit multicycle RISC CPU

A 32-bit MIPS Processor Implementation in Verilog HDL

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A 5-stage, in order, pipelined upgrade of the single-cycle RV32I CPU in SystemVerilog. Includes the RISC-V "M" extension (multiply/divide) with multi-cycle arithmetic units, a full hazard unit with data forwarding and dynamic branch prediction.

Designing and testing a simple Multi-Cycle RISC processor using HDL language (Verilog).