Instruction set simulator for RISC-V, MIPS and ARM-v6m

Online MIPS32 Simulator Based on Spim

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

An unofficial reference implementation of the C Minus Minus Compiler

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

Introducing the new lightweight MIPS Assembler and Disassembler, supporting syntax highlighting, code editing, file dragging and dropping, debug mode, assembly and disassembly, Molokai color matching style. Full platform support including Windows, macOS and Linux. Star now! Keep updating!

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

Provide Gentoo binhosts using github infrastructure

CREATOR is a generic teaching simulator to program in assembly in which you can simulate the operation of different architectures on the same tool. This simulator is designed to be used as a tool in which students can put into practice the brews seen in the theoretical classes of the subjects of Architecture and Computer Structure.

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

Light-weight MIPS R4000 and RISC-V system simulator

Statically compiled binaries for various architectures.

This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.

A VFPU accelerated linear algebra & quaternion library for the PlayStation Portable.

MIPS32 emulation fuzzing

A book on MIPS assembly programming using simulators (MARS, SPIM, QtSpim) targeted at college students.

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

A collection of my cheat codes (ASM hacks) for various games across multiple platforms. This collection includes only codes made by me.

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

Street Fighter II using MIPS and the DE2-70 development kit.

SUSTech CS202/CS214 Computer Organization Project. Streams Bad Apple.

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

𝗖𝗼𝗺𝗽𝘂𝘁𝗲𝗿 𝗢𝗿𝗴𝗮𝗻𝗶𝘇𝗮𝘁𝗶𝗼𝗻 & 𝗔𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁𝘂𝗿𝗲 | 𝗖𝗦𝟯𝟵𝟬𝟬𝟭

Projects that were done for my CS14 (Assembly language) course that used the MIPS assembly language.

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

Buildroot for Halley5, the evaluation board for Ingenic X2000 SoC

MIPS单周期CPU，共支持39条指令