A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

5-stage pipelined 32-bit MIPS microprocessor in Verilog

It's all coming back into focus!

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

No description provided.

A 5-stage pipelined mips32 processor

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.

MIPS simulator written in Go

Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

the tiniest MIPS R4300i assembler and disassembler

DEPRECATED!!! An (almost) fully functional theme engine for MARS.

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

Buildroot for Halley5, the evaluation board for Ingenic X2000 SoC

simulator of a MIPS processor in C

Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the format) and simulates what MIPS does cycle-by-cycle (single-cycle data path).

💻 MIPS Pipeline Processor simulator

A 32-bit MIPS processor developed in Verilog based on pipeline

No description provided.

No description provided.