ESESC: A Fast Multicore Simulator

A Fast DNN Accelerator Design Space Exploration Framework.

My solutions of Computer Systems: A Programmer’s Perspective, Third Edition (CS:APP3e) book, the text book for the course, CMU15-213: Introduction to Computer Systems.

MIT Course 6.004 - Computation Structures

A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for architecture research and education.

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

HHRT: Hybrid Hierarchical Runtime library

Hardware compression for memory

A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies

A superscalar out-of‐order architectural simulator (With Memory Hierarchy).

Implementation of Hierarchy Oblivious Algorithms

A loop test performance simulator for cache memories

No description provided.

(ECE) A collection of helper scripts for the assignments for the course "Advanced Computer Architecture" [3.4.37.8]

The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

A simulator of cache system behavior.

Papyrus: Parallel Aggregate Persistent Storage

CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .

A bash shell script to show information about memory hierarchy. PT-br: Um script shell para mostrar informações sobre a hierarquia de memória.

Assembly MIPS - Pipelined Datapath - Memory Hierarchy - Virtual Memory | Computer Architecture at ECE NTUA

Análise: Influência da organização da memória no desempenho em algoritmos de multiplicação de matriz geral de precisão dupla (DGEMM).

CSE 614 Term Project

ConvolutioninCUDA

Trabalho de OC1 sobre Hierarquia de Memórias. Computer Organization 1 lecture work about Memory Hierarchy.

Memory Hierarchy - Branch Prediction and Predictors - Cache Coherence Protocols | Advanced Topics in Computer Architecture at ECE NTUA

Repository of the lab3 assignment for the Parallel Programming course.

COE758 - This course covers advanced computing systems with emphasis on system architecture, memory hierarchy (Cache, Virtual memory), processor-peripheral interfacing, and bus organization. Laboratory projects include Cache Controller and VGA display design using FPGA. This course is taken at TMU, formally known as Ryerson.

Multi-level cache simulator in C++17 with LRU, write-back, and Markov prefetching