Teaching Materials for Dr. Waleed A. Yousef

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

Water Level Meter

All the homeworks, studies and projects I've done at Metu-CENG

EventNext is logic interface design actors components for .net core

Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.

Logic Minimization in Python

All the homeworks, testers and projects done at METU-CENG

As an Ignite Coder, solved numerous problems using C programming, demonstrating expertise in algorithms, problem-solving, and efficient coding for technical challenges.

SystemVerilog examples for a digital design course

All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Projects of a CSE student at Marmara University

ELVE : ELVE Logic Visualization Engine

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Automated conversion from CHP to PRS

Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

A collection of digital logic circuits

The program in GUI that show and minimize with Karnaugh-Map in Python & C++

Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

A puzzle game for iOS.

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

University of Marmara, CSE3015 2018 Fall Project

4221-to-Seven-Segment Decoder for Logic Design course — A combinational circuit converting custom 4-bit binary inputs into signals to drive a common-cathode 7-segment display, using basic logic gates (NOT, AND, OR).

Practice project to learn basics of backend.

Homeworks given at Department of Computer Engineering, Middle East Technical University.

Educational Project for Logic Design 1 course taken during Fall 2021 semester.

Simple microprocessor in SystemVerilog.

The repository contains all the assignments completed as a course-work of the 4th semester.