HDL support for VS Code

IceChips is a library of all common discrete logic devices in Verilog

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

A place to keep my synthesizable verilog examples.

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

💎 A 32-bit ARM Processor Implementation in Verilog HDL

🎞️ NoC router in Verilog with FIFO

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

No description provided.

使用verilog实现流水线 FFT

This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

Multi-port BRAM IP for ASIC and FPGA

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

a project to check the FOSS synthesizers against vendors EDA tools

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

5-pipe core for RISCV32I

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

This is a documentation of the work done as part of the 5 - day RTL Design Workshop using Verilog with SKY130 Technology

This is a bitty CPU core of risc-v architecture, which is currently under development.

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

☎️ UART Communication Implementation in Verilog HDL

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Sample Verilog codes for digital circuits

16-bit Slansky Adder design using verilog HDL

fibonacci number calculator written in Verilog-HDL